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Burst Transfer with a Slow PCI Master
Burst Transfer with a Slow PCI Master
Figure 6-7 to Figure 6-9 on page 58 show burst transfers with a PCI Master that transfers one word of data every three
clock cycles. The backend in this case is capable of transferring data every clock cycle. The core reads data from the
backend and stores it in the internal FIFO. Figure 6-7 shows seven data words being read from the backend (cycles three
to nine). These words are then transferred on the PCI bus at the rate governed by the PCI Master. The core stores a
maximum of five words internally. By cycle nine, the core has read seven words from the backend and transferred two
words on the PCI bus. It then stops reading data from the backend. When the number of words stored in the core drops
to four, the core starts reading data from the backend again.
Figure 6-8 on page 58 shows the same slow PCI Master reading data from the backend when RD_SYNC = 1. The main
difference here is that the core samples data on the clock edge following the strobe assertion. Since data is transferred a
clock cycle later, the internal FIFO fill level is different than in Figure 6-7 .
In the case of write transfers, the backend logic continuously asserts WR_BE_RDY, indicating it is ready to accept data.
Data is then written to the backend every three clock cycles. The backend address increments after each write completes
( Figure 6-9 on page 58 ).
cycle
0
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15 16
17 18 19
clk
framen
ad[31:0]
ADDR
0
1
2
3
4
cben[3:0]
par
devseln
irdyn
trdyn
dp_start
dp_done
bar_select[2:0]
rd_cyc
rd_stb_out
rd_stb_in
6
0
0
mem_add[11:0]
000
004 008 00C 010 014 018
01C
020
024
mem_data_in[31:0]
0
1
2
3
4
5
6
7
8
rd_sync
Figure 6-7 · Backend Read Cycle with Slow PCI Master (RD_SYNC = 0)
v4.0
57
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